Flash command that reports a count of cell program failures

ABSTRACT

An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.

This application relates to U.S. Ser. No. 14/284,875, filed May 22,2014, which is incorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates to data storage generally and, more particularly,to a method and/or apparatus for implementing a flash command thatreports a count of cell program failures.

BACKGROUND

Conventional flash memory devices define various commands and types ofstatus commands reported to a flash controller. Flash memory vendorsdetermine market trends. Flash memory vendors do not typically designcontrollers and lack a complete view of flash controllers. Somepotentially useful commands are needed that flash memory vendors havenot considered. A flash controller vendor can define necessary anduseful commands that can help to improve system performance. The flashmemory provides basic information on things such as whether a programoperation has failed or not failed. In conventional approaches, flashmemory has been relatively reliable. Even a one bit program failure wasconsidered unacceptable and reported as a program failure. Suchcontrollers increase the cost by not using memory that is usable, buthas errors. Flash controllers implementing error correction code (ECC)decoding are more aggressive and can correct multiple errors percodeword. Improving bit error correction capability will be more andmore necessary as the density of flash memory is increased due to afurther scaled down cell size. A simple reporting of a program failureif just one or two bits fail to be programmed does not provide adequateinformation to a flash controller to be efficient.

It would be desirable to implement a flash command that reports a countof the total number of cell program failures and/or a count of thenumber of cell program failures on a per chunk basis.

SUMMARY

The invention concerns an apparatus comprising a memory and acontroller. The memory configured to store data. The memory may comprisea write buffer and a plurality of memory dies. Each memory die may havea size less than a total size of the memory and include a plurality ofcells. The memory may perform a program operation to write to and verifyone or more of the plurality of cells in response to receiving a programcommand. The controller may be configured to issue the program commandto program the plurality of memory dies and to issue the polling statuscommand after issuing the program command to obtain a number of thecells that failed to be verified during the program operation. Inresponse to the polling status command received from the controller, thememory reports a count of a number of bit-lines not having an inhibitedstate in the write buffer.

BRIEF DESCRIPTION OF THE FIGURES

Embodiments of the invention will be apparent from the followingdetailed description and the appended claims and drawings in which:

FIG. 1 is a diagram illustrating an example embodiment;

FIGS. 2A-2B are diagrams illustrating an example program command;

FIG. 3 is a flow diagram illustrating incremental step pulseprogramming;

FIG. 4 is a diagram of a graph illustrating errors corrected by ECCversus program/erase cycles;

FIG. 5 is a flow diagram illustrating reporting a number of cells thatfail programming;

FIG. 6 is a flow diagram illustrating a decision based on a reportederror count;

FIG. 7 is a flow diagram illustrating issuing polling status commands;and

FIG. 8 is a flow diagram illustrating reporting a number of cells thatfail programming using a single buffer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention include providing a flash command thatreports a count of cell program failures that may (i) implement apolling status command to verify cell programming, (ii) report a totalnumber of cells that failed programming, (iii) provide error reportingon a per chunk basis, (iv) leverage information traditionally availablein flash memory, (v) determine the number of errors without triggering aread operation, (vi) reprogram data to known reliable locations if thenumber of errors is above a threshold, (vii) tolerate errors if thenumber of errors is below a threshold, (viii) report a total number ofcells that failed programming as a chunk of cells, and/or (ix) beimplemented as one or more integrated circuits.

Flash memory modules generally provide information on whether a programoperation has failed or did not fail. Basic information on whether theprogram operation failed or did not fail may be acceptable when theflash memory has high target reliability. With flash memory having highreliability, a one or two bit correction Hamming code may be applied. Ina high target reliability configuration without further errorcorrection, even a one bit program failure would be unacceptable and astatus report indicating a program failure would provide sufficientinformation to a flash controller. For example, with a Hammingcode-based Solid State Drive (SSD) controller, if the flash memoryreports a program failure (e.g., a one bit failure), the existingprogram operation would be discarded and the data could be programmed toother reliable locations.

A flash controller (e.g., an SSD controller) may implement ECC capableof correcting multiple errors per codeword. ECC may correct errors inless reliable flash memory. For example, a 40-bit error correctioncapability per 1 k byte ECCs may be implemented for a 20 nm MLC NANDflash memory. As flash memory is scaled down, more errors are expected,and more bit error correction capability is generally needed. Since ECCis capable of correcting multiple errors per codeword, a basic report ofa program failure based on one or two bits that fail to be programmedmay not provide sufficient information to a SSD controller. For example,a SSD controller may be able to tolerate more than one or two bits(e.g., cells) that fail to be programmed if the number of bits havingerrors were below a correctable amount.

Referring to FIG. 1, a block diagram of an example apparatus 50 isshown. The apparatus 50 generally comprises a block (or circuit) 60, ablock (or circuit) 70 and a block (or circuit) 80. The circuit 70 mayinclude a circuit 100. The circuit 100 may be a memory/processorconfigured to store computer instructions (or firmware) or may be logic.The instructions, when executed, may perform a number of steps. Thefirmware 100 may include a redundancy control module 110. The redundancycontrol module 110 may be implemented as part of the firmware 100 or asa separate module. While an example of redundancy implemented in thefirmware 100 is shown, the redundancy may be implemented, in anotherexample, in hardware (e.g., logic such as a state machine).

A signal (e.g., REQ) may be generated by the circuit 60. The signal REQmay be received by the circuit 70. The signal REQ may be a requestsignal that may be used to access data from the circuit 80. A signal(e.g., I/O) may be generated by the circuit 70 to be presented to/fromthe circuit 80. The signal REQ may include one or more address bits. Asignal (e.g., DATA) may be one or more data portions received by thecircuit 60.

The circuit 60 is shown implemented as a host circuit. The circuit 70reads and writes data to and from the circuit 80. The circuit 80 isgenerally implemented as a nonvolatile memory circuit. The circuit 80may include a write buffer 86 a, a verify/read buffer 86 b, a comparator88, and a number of modules 82 a-82 n. The modules 82 a-82 n may beimplemented as NAND flash chips. In some embodiments, the circuit 80 maybe a NAND flash device. In other embodiments, the circuit 70 and/or thecircuit 80 may be implemented as all or a portion of a solid state drive90 having one or more nonvolatile devices. The circuit 80 is generallyoperational to store data in a nonvolatile condition. When data is readfrom the circuit 80, the circuit 70 may access a set of data (e.g.,multiple bits) identified in the signal REQ. The signal REQ may requestdata from the drive 90 or from one of a number of additional storagedevices.

Data within the circuit 80 is generally organized in a hierarchy ofunits, such as die, plane, block, and/or page units. The units may becomprised of cells. The circuit 80 may contain multiple dies (e.g., in asingle package or multiple packages). Generally, for enterpriseapplications the circuit 80 may be comprised of hundreds of flash memorydies. Flash memory may have multiple planes in the same die. The planesmay be accessed in parallel to improve performance.

A first type of redundancy may be implemented as a redundancy block. Aredundancy block is a combination of blocks (e.g., a block from eachnonvolatile memory die in the circuit 80) that can be combined to form aredundant array of silicon independent elements, similar to a redundantarray of independent disks for magnetic media. The nonvolatile memorylocations within the blocks may be written in a striped fashion. In someembodiments, organizing a plurality of blocks in redundancy blocksreduces an overhead of block management. A block is generally considereda smallest quantum of erasing. A page is generally considered a smallestquantum of writing. A read unit (or codeword or Epage or ECC-page) is asmallest correctable quantum of reading and/or error correction. Eachblock includes an integer number of pages. Each page includes an integernumber of read units.

In some embodiments, the circuit 80 may be implemented as a single-levelcell (e.g., SLC) type circuit. A SLC type circuit generally stores asingle bit per memory cell (e.g., a logical 0 or 1). In otherembodiments, the circuit 80 may be implemented as a multi-level cell(e.g., MLC) type circuit. A MLC type circuit is generally capable ofstoring multiple (e.g., two) bits per memory cell (e.g., logical 00, 01,10 or 11). In still other embodiments, the circuit 80 may implement atriple-level cell (e.g., TLC) type circuit. A TLC circuit may be able tostore multiple (e.g., three) bits per memory cell (e.g., a logical 000,001, 010, 011, 100, 101, 110 or 111). In yet another embodiment, thecircuit 80 may implement a circuit with a cell level greater than atriple-level cell. Generally, the circuit 80 may be implemented as ann-level cell capable of storing n-bits per memory cell.

In general, the controller 70 may include an erase/program unit that mayimplement redundancy across the modules 82 a-82 n. For example, multipleblocks may be read from multiple dies 82 a-82 n. The erase/program unitmay be implemented as part of the firmware (or logic) 100.

The drive 90 may contain, in one example, multiple NAND Flash or memorymodules 82 a-82 n. Each of the memory modules 82 a-82 n may befabricated as one or more dies (e.g., 1, 2, 4, 8, etc.). The dies (ormodules) 82 a-82 n may operate to read or to write concurrently. Theread and write bandwidth depends on how many of the dies 82 a-82 n areimplemented, as well as the bandwidth of each of the dies 82 a-82 n.Each of the dies 82 a-82 n may contain a plurality of planes. Each ofthe planes of the dies 82 a-82 n may contain a plurality of blocks 84a-84 n. The blocks 84 a-84 n of the planes of one of the dies 82 a-82 nmay be accessed in parallel. If the SSD 90 receives the host commandREQ, in order to achieve the best performance, and/or to address wearleveling issues, the drive 90 will walk through all of the dies 82 a-82n (e.g., a first page of DIE0, DIE1 . . . DIEn, then a next page ofDIE0).

The write buffer 86 a may buffer error free data to be programmed to thecircuit 80. For example, the signal I/O may present data from thecontroller 70 to the circuit 80. The data in the signal I/O may bestored in the write buffer 86 a. Data stored in the write buffer 86 amay be programmed to the memory units (e.g., the memory modules 82 a-82n, and/or the memory blocks 84 a-84 n). Data stored in the write buffer86 a may be stored temporarily (e.g., until the data is programmed tothe cells in the memory 80 and/or until the program operation success isverified).

The verify/read buffer 86 b may store read out data (e.g., verify data).The read out data stored in the verify/read buffer 86 b may be used toverify the success of a program operation. For example, the verify/readbuffer 86 b may be configured to read cells during a verify stage ofincremental step pulse programming (ISPP).

The comparator 88 may be configured to compare values presented by thewrite buffer 86 a and the verify/read buffer 86 b. For example, thecomparator 88 may compare values from the write buffer 86 a and theverify/read buffer 86 b bit by bit. A bit by bit comparison maydetermine the location and/or number of cells that have programerrors/failures.

The arrangement and interconnections of the write buffer 86 a, theverify/read buffer 86 b, and the comparator 88 may be varied accordingto the design criteria of a particular implementation. For example, insome embodiments, the memory 80 may be comprised of the write buffer 86a, the verify/read buffer 86 b, and/or the comparator 88. In anotherexample, the memory 80 may be comprised of only a single buffer (e.g.,the write buffer 86 a). In yet another example, other buffers and/orcomparison circuits may be implemented. A number of cells that haveprogramming errors/failures may be determined based on the arrangementof circuits in the memory 80.

Referring to FIGS. 2A-2B, a diagram illustrating an example programcommand is shown. Various cycle types are shown. The cycle types may bevaried according to the design criteria of a particular implementation.Generally, the controller 70 may issue a program command (e.g., 80H).The program command may be issued to the flash memory 80. Afterprogramming data to the flash memory 80, the controller 70 may verifythe program operation. In conventional SSD controllers, the programverify may be implemented by issuing a read status command (e.g., 70H)to the flash memory 80 to report a programming failure. In conventionalSSD controllers, a program failure may be reported if any of the cellsare not successfully programmed. However, additional errors may betolerated.

Flash memory cells are programmed with ISPP. ISPP generally comprisestwo stages. A program stage may increase a threshold voltage by ΔV ofthe cells that are programmed. The verify stage may read the programmedcells to determine whether the threshold voltage is larger than a targetthreshold voltage. For example, the verify/read buffer 86 b may read theprogrammed cells. If the threshold voltage is larger than the targetthreshold voltage, ISPP may terminate programming. If the thresholdvoltage is less than the target threshold voltage, ISPP may repeatiterations of the program stage and/or the verify stage. Iterations maybe repeated until a maximum number of such iterations (e.g., a loopcount) has been reached, and/or until the ISPP terminates because all ofthe cells are correctly programed.

In a conventional SSD, if the flash memory 80 reaches the maximumprogram/verify loop count, the flash memory 80 may determine whether allof the cells have reached the target threshold voltage range. In aconventional SSD, if all the cells reach the target threshold voltagerange, the flash memory 80 may report programming success after the readstatus command (e.g., 70H). In a conventional SSD, if all of the cellsdo not reach the target threshold voltage range, the flash memory 80 mayreport a program failure after the read status command.

The controller 70 may be configured to perform a polling status command.The polling status command may be performed instead of the read statuscommand. The polling status command may report to the controller 70 anumber of bits and/or cells that failed to be programed. If the bitand/or cell failure count is less than a tolerable amount, thecontroller 70 may tolerate the errors and/or programming failures. Thepolling status command may request a report from the flash memory 80 toindicate the number of cells that failed to be programmed.

Referring to FIG. 3, a flow diagram illustrating a method (or process)200 is shown. The method 200 may implement incremental step pulseprogramming. The method 200 generally comprises a step (or state) 202, astep (or state) 204, a step (or state) 206, a step (or state) 208, adecision step (or state) 210, a step (or state) 212, a step (or state)214, a decision step (or state) 216, and a step (or state) 218. Thesteps 204 and/or 206 may be the program stage. The steps 208, 210, 212,216 and/or 218 may be the verify stage.

The state 202 may be a start state. The state 204 may increase thethreshold voltage by a value ΔV. The state 206 may program a number ofcells with the threshold voltage. The state 208 may read one or morecells. The decision state 210 may determine whether a cell has a voltagegreater than a target voltage. If so, the method 200 moves to the state212. The state 212 may report a program success. Next, the method 200moves to the state 214, which ends the method 200.

If the decision state 210 determines a cell does not have a voltagegreater than a target voltage, the method 200 moves to the decisionstate 216. The decision state 216 may determine if a maximum number ofiterations has been reached. If so, the method 200 moves to the state218. If not, the method 200 moves back to the state 204. The state 218reports a program failure. Next, the method 200 ends at the state 214.

Referring to FIG. 4, a diagram of a graph illustrating errors correctedby ECC versus program/erase cycles is shown. Current NAND flash memory(e.g., the memory 80) may show failures after programming even at lowP/E cycles. For example, the errors corrected by the ECC codes shown inFIG. 4 indicate errors at low P/E cycles. The conventional read statuscommand may indicate programming failure at low P/E cycles. However,since the ECC codes shown in FIG. 4 may be capable of correcting theerrors, the number of errors may be tolerable. When the number of errorsis tolerable, the conventional read status command may not provideuseful information. For example, the conventional read status commandmay report a programming failure even when the number of errors istolerable. The information provided by the conventional read statuscommand may be unnecessary and/or have little or no value.

Generally, detailed information regarding the number of cells thatfailed programming is useful. To determine the number of cells thatfailed programming, the conventional SSD controller may read a completepage and compare the read data with the known programmed data.Performing additional read operations may significantly degrade theperformance of the SSD 90.

The polling status command may be implemented by the controller 70. Thepolling status command may report the number of errors (e.g., the numberof cells that failed after a programming operation) without performingan additional read operation. For example, the comparator 88 may providethe number of errors by performing a bit by bit comparison of datastored in the write buffer 86 a and the verify/read buffer 86 b. Thepolling status command may leverage information available from the flashmemory 80. The polling status command may increase the performance ofthe SSD 90. Based on the number of errors reported by the polling statuscommand, the controller 70 may take further steps to ensure integrity ofthe data.

Referring to FIG. 5, a flow diagram illustrating a method (or process)280 is shown. The method 280 may implement reporting a number of cellsthat fail programming. The method 280 generally comprises a step (orstate) 282, a step (or state) 284, a decision step (or state) 286, astep (or state) 288, a step (or state) 290, a step (or state) 292, astep (or state) 294, and a step (or state) 296.

The state 282 may be a start state. The state 284 may perform ISPP.Next, the decision state 286 determines if ISPP has reached the lastverify step. If not, the method moves back to the state 284. If so, themethod 280 moves to the state 288. The state 288 retrieves bufferederror free data from the flash memory (e.g., data stored in the writebuffer 86 a). Next, the state 290 retrieves verify data from the flashmemory 80 (e.g., data stored in the verify/read buffer 86 b). Next, thestate 292 compares the buffered error free data to the verify data(e.g., a bit by bit comparison performed by the comparator 88). Next,the state 294 reports the number of errors from the compare step 292.The state 296 ends the method 280.

In response to the status polling command, the flash memory 80 mayreport the number of cells that failed programming (e.g., the number oferrors). ISPP may be implemented to program/verify the flash cells ofthe flash memory 80. The flash memory 80 may store buffered, error freedata in the write buffer 86 a to be programmed in the flash memorycells. The flash memory may have read out data (e.g., verify data)stored in the verify/read buffer 86 b after programming.

In the last verify steps of ISPP, the comparator 88 may compare theverify/read data stored in the verify/read buffer 86 b to the buffereddata (e.g., the data to be programmed) stored in the write buffer 86 a(e.g., a bit by bit comparison). The comparison performed by the flashmemory 80 may determine the number of cells that failed to beprogrammed. Generally, flash memory is already configured to read/verifydata and/or buffer error free data that needs to be programmed. Thecontroller 70 implementing the status polling command may leveragefunctionality in the flash memory 80 to determine whether or not theprogram operation may be considered successful or unsuccessful.

Referring to FIG. 6, a flow diagram illustrating a method (or process)300 is shown. The method 300 may implement a decision based on areported error count. The method 300 generally comprises a step (orstate) 302, a decision step (or state) 304, a step (or state) 306, astep (or state) 308, a step (or state) 310, a decision step (or state)312, a step (or state) 314, a step (or state) 316, a step (or state)318, a step (or state) 320, and a step (or state) 322.

The state 302 starts the method 300. Next, the decision state 304determines whether a program operation has been issued. If so, themethod 300 moves to the state 308. If not, the method 300 moves to thestate 306, which ends the method 300. The state 308 issues a pollingstatus command. Next, the state 310 reports an error count. Next, themethod 300 moves to the decision state 312.

The decision state 312 determines if the number of errors is above athreshold. If not, the method 300 moves to the state 314. The state 314allows the controller 70 to tolerate the measured error count. Next, thestate 316 reports a success of the programming. The method 300 then endsat the state 306. If the decision state 312 determines the number oferrors is above the threshold, the method 300 moves to the state 318.The state 318 reprograms data to another location. Next, the state 320reports a failure of the programming. The state 322 ends the method 300.

Referring to FIG. 7, a flow diagram illustrating a method (or process)350 is shown. The method 350 may implement issuing polling statuscommands. The method 350 generally comprises a step (or state) 352, adecision step (or state) 354, a step (or state) 356, a decision step (orstate) 358, a step (or state) 360, a step (or state) 362, a step (orstate) 364, a decision step (or state) 366, and a step (or state) 368.The step 352 starts the method 350. The decision state 354 determines ifa program operation has been issued. If not, the method 350 moves to thestate 356, which ends the method 350. If so, the method 350 moves to thedecision state 358.

The decision state 358 determines whether a report of the total numberof failed cells is requested. If so, the method 350 moves to the state360. The state 360 issues a polling status command number 1. Next, thestate 362 reports the total number of cells that failed programming. Themethod then ends at the state 356. If the decision state 358 determinesa report of the total number of failed cells is not requested, themethod 350 moves to the state 364. The state 364 issues a polling statuscommand number 2. Next, the decision state 366 determines if there aremore chunks of cells in a page. If not, the method 350 moves to thestate 356 which ends the method 350. If so, the method 350 moves to thestate 368. The state 368 reports the number of cells that failedprogramming in the next chunk. The method 350 then returns to thedecision state 366.

Referring to FIG. 8, a flow diagram illustrating a method (or process)400 is shown. The method 400 may implement reporting a number of cellsthat fail programming using a single buffer. The method 400 generallycomprises a step (or state) 402, a step (or state) 404, a decision step(or state) 406, a step (or state) 408, a step (or state) 410, a step (orstate) 412, a step (or state) 414, a decision step (or state) 416, adecision step (or state) 418, a step (or state) 420, a step (or state)422, a decision step (or state) 424, and a step (or state) 426.

The state 402 may start the method 400. The state 404 may begin ISPP.Next, the method 400 moves to the decision state 406. If the decisionstate 406 determines there are not more cells to program, the method 400moves to the state 408. The state 408 may count a number of bit-linesnot in an inhibited state. Next, the state 410 may report the number ofbit-lines not in the inhibited state as errors. Next, the method 400moves to the state 412, which ends the method 400. If the decision state406 determines there are more cells to program, the method 400 moves tothe state 414. The state 414 may go to the next memory unit. Next, themethod 400 moves to the decision state 416.

If the decision state 416 determines the bit-line is set to theinhibited state, the method 400 returns to the decision state 406. Ifnot, the method 400 moves to the decision state 418. If the decisionstate 418 determines the maximum number of iterations has been reached,the method 400 returns to the decision state 406. If not, the method 400moves to the state 420.

The state 420 may program the cells (e.g., the program stage of ISPP).The state 422 may re-read the cells (e.g., the verify stage of ISPP).Next, the method 400 moves to the decision state 424. If the decisionstate 424 determines the program was not successful, the method 400returns to the decision state 418. If the decision state 424 determinesthe program was successful, the method 400 moves to the state 426. Thestate 426 may set the corresponding bit-line to the inhibited state.Next, the method 400 returns to the decision state 406.

In some embodiments, ISPP may be implemented with a single write databuffer (e.g., the write buffer 86 a). One bit buffer may correspond toone bit-line (e.g., an all bit-line architecture), or one bit buffer maybe shared between two neighbor bit-lines (e.g., an even/oddarchitecture). During ISPP, the flash memory 80 may program the flashcells. The flash cells in a memory unit may be programmed simultaneously(e.g., the flash cells in a page may be programmed simultaneously).After programming the flash cells, the flash memory 80 may re-read theflash cells. If the programming is successful (e.g., the cell voltage isgreater than the target voltage), data stored in the write buffer 86 awill be changed to an inhibited state. For example with SLC memory, thewrite bit may be set to a logical 1. In another example with MLC memory,the write bit may be set to a logical 11.

Cells on corresponding bit-lines having an inhibited state in the writebuffer 86 a may not be programmed. If a program operation isunsuccessful, the cells on corresponding bit-lines may not have aninhibited state in the write buffer 86 a. Cells not having correspondingbit-lines with an inhibited state may be reprogrammed (e.g., anotheriteration of ISPP may be performed).

After ISPP is completed, the number of bit-lines in an inhibited statein the write buffer 86 a may be counted. For example, if a programoperation is completed successfully (e.g., no cells have failedprogramming), then all bit-lines in the write buffer 86 a may beinhibited. In another example, if there are some bit-lines not in aninhibited state, then some cells may not be sufficiently programmed(e.g., there was a program failure). For example, if the data value inthe sense amplifier of each bit-line is not logical 1 for SLC memory ornot logical 11 for MLC memory, then there may be a programming error.

The number of bit-lines not in the inhibited state in the write buffer86 a may correspond to the number of programming errors. A count of thenumber of bit-lines in the write buffer 86 a that are not in theinhibited state after ISPP is completed may report the number of errors.Counting the number of bit-lines may be performed per physical flashpage and/or per chunk (e.g., codeword and/or fragment of a flash page).For example, the count of the number of bit-lines in the write buffer 86a may be performed on a chunk of memory when there are 8 and/or 16codewords per flash page.

Once the flash controller 70 knows the error count due to programfailure(s) and/or the error count in a chunk of cells inside a page, thecontroller 70 may make a decision on the next steps to perform (e.g.,steps to ensure data integrity). In one example where the error count ishigh (e.g., above an error correction capability of ECC), the controller70 may reprogram data in other locations. In another example where theerror count is low (e.g., below an error correction capability of ECC),the controller 70 may tolerate the errors.

The controller 70 may implement various polling status commands. In someembodiments, the controller 70 may implement the polling status commandnumber 1. The polling status command number 1 may report the totalnumber of failed cells of one page. For example, the controller 70 mayissue the polling status command number 1 after a program operation andthe flash memory circuit 80 may report the total number of cells thatfailed to be programmed in a current page.

In some embodiments, the controller 70 may implement the polling statuscommand number 2. The polling status command number 2 may report thetotal number of failed cells of each chunk of cells inside a page. Forexample, the flash controller 70 may issue the polling status commandnumber 2 after a program operation and the flash memory circuit 80 mayreport the total number of cells that failed to be programmed in eachchunk of a page.

A flash page may be divided into codewords. A chunk of a page may be acodeword. For example, a 16 k byte flash page may be divided into 8codewords where each codeword may be 2 k bytes and each codewordcorresponds to 16 k cells. When the controller 70 issues the pollingstatus command number 2, the flash memory 80 may report the total numberof cells that fail programming in each 16 k section of cells (e.g., thenumber of cells that failed programming in a codeword/chunk).

In some embodiments, the controller 70 may implement the polling statuscommand number 1 and/or the polling status command number 2. By issuingthe polling status command(s), the flash controller 70 may be presentedwith the cell failure count just by status polling (e.g., withoutissuing a read command). Status polling may be faster (e.g., by ordersof magnitude) than reading a whole page that was programmed andcomparing the read data with the original data sent to be programmed.

The total number of failed cells reported by implementing the pollingstatus command may provide the flash controller 70 with sufficientinformation to determine efficient data management procedures. Forexample, the controller 70 may determine whether to reprogram data toother locations (e.g., locations that are known to be reliable). Inanother example, the controller 70 may determine whether or not to keepthe existing programmed data.

In some embodiments, the controller 70 may adjust a refresh frequency ofthe cells in locations having a tolerable error count. The refreshfrequency may be increased to ensure that the total number of errors iswithin the error correction capability of ECC. For example, for alocation having a high number of program errors, increasing the refreshfrequency may lower the number of errors at the end of the refreshperiod. The total number of errors may be the sum of the program errors,other errors, and/or retention errors. Increasing the refresh frequencymay control the number of retention errors. Increasing the refreshfrequency may allow a block and/or flash page to still be usable. Sincethe flash controller 70 implements ECC capable of correcting a number oferrors, one or just a few cells that fail programming may be tolerable.

The functions performed by the diagrams of FIGS. 3 and 5-8 may beimplemented using one or more of a conventional general purposeprocessor, digital computer, microprocessor, microcontroller, RISC(reduced instruction set computer) processor, CISC (complex instructionset computer) processor, SIMD (single instruction multiple data)processor, signal processor, central processing unit (CPU), arithmeticlogic unit (ALU), video digital signal processor (VDSP) and/or similarcomputational machines, programmed according to the teachings of thespecification, as will be apparent to those skilled in the relevantart(s). Appropriate software, firmware, coding, routines, instructions,opcodes, microcode, and/or program modules may readily be prepared byskilled programmers based on the teachings of the disclosure, as willalso be apparent to those skilled in the relevant art(s). The softwareis generally executed from a medium or several media by one or more ofthe processors of the machine implementation.

The invention may also be implemented by the preparation of ASICs(application specific integrated circuits), Platform ASICs, FPGAs (fieldprogrammable gate arrays), PLDs (programmable logic devices), CPLDs(complex programmable logic devices), sea-of-gates, RFICs (radiofrequency integrated circuits), ASSPs (application specific standardproducts), one or more monolithic integrated circuits, one or more chipsor die arranged as flip-chip modules and/or multi-chip modules or byinterconnecting an appropriate network of conventional componentcircuits, as is described herein, modifications of which will be readilyapparent to those skilled in the art(s).

The invention thus may also include a computer product which may be astorage medium or media and/or a transmission medium or media includinginstructions which may be used to program a machine to perform one ormore processes or methods in accordance with the invention. Execution ofinstructions contained in the computer product by the machine, alongwith operations of surrounding circuitry, may transform input data intoone or more files on the storage medium and/or one or more outputsignals representative of a physical object or substance, such as anaudio and/or visual depiction. The storage medium may include, but isnot limited to, any type of disk including floppy disk, hard drive,magnetic disk, optical disk, CD-ROM, DVD and magneto-optical disks andcircuits such as ROMs (read-only memories), RAMs (random accessmemories), EPROMs (erasable programmable ROMs), EEPROMs (electricallyerasable programmable ROMs), UVPROM (ultra-violet erasable programmableROMs), Flash memory, magnetic cards, optical cards, and/or any type ofmedia suitable for storing electronic instructions.

The elements of the invention may form part or all of one or moredevices, units, components, systems, machines and/or apparatuses. Thedevices may include, but are not limited to, servers, workstations,storage array controllers, storage systems, personal computers, laptopcomputers, notebook computers, palm computers, personal digitalassistants, portable electronic devices, battery powered devices,set-top boxes, encoders, decoders, transcoders, compressors,decompressors, pre-processors, post-processors, transmitters, receivers,transceivers, cipher circuits, cellular telephones, digital cameras,positioning and/or navigation systems, medical equipment, heads-updisplays, wireless devices, audio recording, audio storage and/or audioplayback devices, video recording, video storage and/or video playbackdevices, game platforms, peripherals and/or multi-chip modules. Thoseskilled in the relevant art(s) would understand that the elements of theinvention may be implemented in other types of devices to meet thecriteria of a particular application.

The terms “may” and “generally” when used herein in conjunction with“is(are)” and verbs are meant to communicate the intention that thedescription is exemplary and believed to be broad enough to encompassboth the specific examples presented in the disclosure as well asalternative examples that could be derived based on the disclosure. Theterms “may” and “generally” as used herein should not be construed tonecessarily imply the desirability or possibility of omitting acorresponding element.

While the invention has been particularly shown and described withreference to embodiments thereof, it will be understood by those skilledin the art that various changes in form and details may be made withoutdeparting from the scope of the invention.

1. An apparatus comprising: a memory configured to store data, thememory comprising a write buffer and a plurality of memory dies, whereineach memory die has a size less than a total size of the memory andincludes a plurality of cells, the memory performs a program operationto write to and verify one or more of the plurality of cells in responseto receiving a program command, and the memory determines and reports anumber of the cells that failed to be verified during the programoperation in response to receiving a polling status command; and acontroller configured to issue the program command to program theplurality of memory dies and to issue the polling status command afterissuing the program command to obtain the number of the cells thatfailed to be verified during the program operation, wherein in responseto the polling status command received from the controller, the memoryreports a count of a number of bit-lines not having an inhibited statein the write buffer.
 2. The apparatus according to claim 1, wherein inthe inhibited state is represented by a write bit of the write bufferhaving a value of logical 1 when the memory is comprised of single-levelcell memory.
 3. The apparatus according to claim 2, wherein in theinhibited state is represented by a write bit of the write buffer havinga value of logical 11 when the memory is comprised of multi-level cellmemory.
 4. The apparatus according to claim 1, wherein the controller isenabled to issue the polling status command having either a first modeconfigured to request the memory report a total number of the cells thatfailed to be programmed in the memory die or a second mode configured torequest the memory report the total number of the cells that failed tobe programmed in a chunk of the memory die.
 5. The apparatus accordingto claim 4, wherein in response to the mode of the polling statuscommand received from the controller, the memory determines the numberof the cells that failed to be verified in the requested portion of thememory die using the number of bit-lines not having an inhibited statein the write buffer corresponding to the requested portion of the memorydie.
 6. The apparatus according to claim 1, wherein said count is atotal number of the cells that failed to be programmed in the memorydie.
 7. The apparatus according to claim 1, wherein said count is atotal number of the cells that failed to be programmed in a chunk of thememory die.
 8. The apparatus according to claim 9, wherein the chunk ofthe memory die is a codeword.
 9. The apparatus according to claim 1,wherein the controller is configured to determine the number ofbit-lines not having an inhibited state in the write buffer withouttriggering a read operation.
 10. The apparatus according to claim 1,wherein the controller is further configured to determine if the numberof the cells that failed to be programmed is above a threshold value.11. The apparatus according to claim 12, wherein the threshold value isan error correcting capability of an error correcting code.
 12. Theapparatus according to claim 11, wherein said controller is furtherconfigured to re-program data stored in the memory to other locations ofthe memory if the number of the cells that failed to be programmed isabove the threshold value.
 13. The apparatus according to claim 11,wherein the controller is further configured to adjust a refreshfrequency of the memory units if the number of the cells that failed tobe programmed is above the threshold value.
 14. The apparatus accordingto claim 11, wherein the controller is further configured to toleratethe number of the cells that failed to be programmed if the number ofthe cells that failed to be programmed is below the threshold value. 15.The apparatus according to claim 1, wherein the apparatus comprises asolid state drive (SSD).
 16. The apparatus according to claim 1, whereinthe controller and the memory are implemented as two or more integratedcircuits.
 17. A method of reporting a count of cell program failures,comprising the steps of: configuring a memory to store data, the memorycomprising a write buffer and a plurality of memory dies, wherein eachmemory die has a size less than a total size of the memory and includesa plurality of cells, the memory performs a program operation to writeto and verify one or more of the plurality of cells in response toreceiving a program command, and the memory determines and reports anumber of the cells that failed to be verified during the programoperation in response to receiving a polling status command; issuing theprogram command to the memory for the program operation to write to andverify one or more of the cells; and issuing the polling status commandto the memory after the program command to obtain a count of a number ofbit-lines not having an inhibited state in the write buffer of thememory.
 18. The method according to claim 17, wherein issuing thepolling status command further comprises: in a first mode, the pollingstatus command is configured to request the memory report a total numberof the cells that failed to be programmed in the memory die; in a secondmode, the polling status command is configured to request the memoryreport the total number of the cells that failed to be programmed in achunk of the memory die; and in response to the mode of the pollingstatus command, the memory determines the number of bit-lines not havingan inhibited state in the write buffer corresponding to the requestedportion of the memory die.
 19. An apparatus comprising: an interfaceconfigured to process a plurality of read/program operations to/from amemory comprising a write buffer and a plurality of memory dies; and acontrol circuit configured to (i) issue a program command to the memoryfor a program operation to write to and verify one or more cells of thememory, and (ii) issue a polling status command to the memory after theprogram command to obtain a number of the cells that failed to beverified during the program operation, wherein in response to thepolling status command received from the control circuit, the memoryreports a count of a number of bit-lines not having an inhibited statein the write buffer.
 20. The apparatus according to claim 19, wherein:the control circuit is enabled to issue the polling status command in afirst mode to request the memory report a total number of the cells thatfailed to be programmed in the memory die; the control circuit isenabled to issue the polling status command in a second mode configuredto request the memory report the total number of the cells that failedto be programmed in a chunk of the memory die; and in response to themode of the polling status command received from the control circuit,the memory determines the number of the cells that failed to be verifiedin the requested portion of the memory die using the number of bit-linesnot having an inhibited state in the write buffer corresponding to therequested portion of the memory die.